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19-5199; rev 4; 1/15 typical application circuit general description the MAX9633 is a low-noise, low-distortion operational amplifier that is optimized to drive adcs for use in appli - cations from dc to a few mhz. the MAX9633 features low noise (3nv/ hz at 1khz and 3.5nv/ hz at 100hz) and low distortion (130db at 10khz), making it suitable for industrial, medical, and test applications. the exceptionally fast settling-time and low input offset voltage makes the ic an excellent solution to drive high- resolution 12-bit to 18-bit sar adcs. the ic operates from a wide supply voltage range up to 36v with only 3.5ma of quiescent current per amplifier. the ic is offered in an 8-pin, 3mm x 3mm tdfn package for operation over the -40 n c to +125 n c temperature range. applications adc drivers data acquisition and instrumentation power grid systems motor control test and measurement equipments imaging systems high-performance audio circuitry benefits and features s high-resolution adc driver 27mhz gain bandwidth 750ns settling time to 16-bit accuracy thd of 130db at 10khz low input voltage offset 200v (max) 3nv/ hz ultra-low input voltage noise low input offset temperature drift 0.9v/c (max) unity gain stable s support a wide range of industrial applications 4.5v to 36v wide supply range s improved reliability 5kv esd protection hbm s saves board space 8-pin tdfn and so packages ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. anti-alias filter c in rr 1mi +15v -15v r2 r1 12 to 18-bit sar adc example: max1320 14-bit adc -3db at 8mhz r i = 20i c = 1nf c MAX9633 part temp range pin- package top mark MAX9633asa+ -40 n c to +125 n c 8 so-ep* MAX9633ata+ -40 n c to +125 n c 8 tdfn-ep* bmm dual 36v op amp for 18-bit sar adc front-end MAX9633 evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc to v ee ) ................................. -0.3v to +40v all other pins .................................. (v ee - 0.3v) to (v cc + 0.3v) short-circuit duration of outa, outb ................................. 10s continuous input current (any pins) ............................... 20ma continuous power dissipation (t a = +70 n c) so (derate 24.4mw/ n c above +70 n c) multilayer board ..................................................... 1951.2mw tdfn (derate 24.4mw/ n c above +70 n c) multilayer board ........................................................ 1905mw operating temperature range ........................ -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v cc = +15v, v ee = -15v, v cm = 0v, r l = 10k i to v gnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-lay - er board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . so-ep junction-to-ambient thermal resistance ( q ja ) .......... 41c/w junction-to-case thermal resistance ( q jc ) ................. 7c/w tdfn-ep junction-to-ambient thermal resistance ( q ja ) .......... 42c/w junction-to-case thermal resistance ( q jc ) ................. 8c/w package thermal characteristics ( note 1) parameter symbol conditions min typ max units power supply supply voltage rang e v cc - v ee guaranteed by psrr 4.5 36 v supply current i cc per amplifier t a = +25 n c 3.5 5 ma -40 n c p t a p +85 n c 6 -40 n c p t a p +125 n c 6.5 power-supply rejection ratio psrr +4.5v p (v cc - v ee ) p +36v t a = +25 n c 112 135 db -40 n c p t a p +125 n c 110 dc specifications input offset voltage v os t a = +25 n c q 70 q 200 f v -40 n c p t a p +125 n c q 290 input offset voltage drift (note 3) d v os -40 n c p t a p +125 n c 0.2 0.9 f v/ n c input bias current i b (v ee + 0.45v) p v cm p (v cc - 1.8v) q 42 q 400 na v ee p v cm p (v cc - 1.8v) 4.5 22 f a input offset current i os (v ee + 0.45v) p v cm p (v cc - 1.8v) q 30 q 300 na v ee p v cm p (v cc - 1.8v) q 200 q 2000 input voltage range v in+ , v in- guaranteed by cmrr t a = +25 n c v ee v cc - 1.7 v -40 n c p t a p +125 n c v ee v cc - 1.8 common-mode rejection ratio cmrr v ee p v cm p (v cc - 1.7v), t a = +25 n c 106 130 db v ee p v cm p (v cc - 1.8v), -40 n c p t a p +125 n c 105 130 maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
3 electrical characteristics (continued) (v cc = +15v, v ee = -15v, v cm = 0v, r l = 10k i to v gnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: all devices are 100% production tested at t a = +25 n c. temperature limits are guaranteed by design. note 3: guaranteed by design. parameter symbol conditions min typ max units open-loop gain a vol (v ee + 0.3v) p v out p (v cc - 2v), r l = 10k i 118 140 db (v ee + 0.45v) p v out p (v cc - 2.1v), r l = 1k i 115 138 output voltage swing v oh v cc - v out r l = 10k i 1.6 1.9 v r l = 1k i 1.7 2.0 v ol v out - v ee r l = 10k i 70 150 mv r l = 1k i 170 300 r l = 10k i to v ee 20 100 r l = 1k i to v ee 20 100 short-circuit current i sc t a = +25 n c 50 ma ac specifications gain bandwidth gbwp 27 mhz slew rate sr 5v step, r s = 20 i , c l = 1nf, a v = 1v/v 18 v/ f s output transient recovery time t tr to 0.001%, d v out = 200mv, r s = 20 i , c l = 1nf, av = +1v/v 500 ns settling time t s to 0.001%, 5v step, av = -1v/v r s = 100 i , c l = 30pf 750 ns r s = 20 i , c l = 1nf 750 total harmonic distortion thd v out = 10v p-p , r s = 20 i , c l = 1nf, a v = +1v/v f = 1khz 145 db f = 10khz 130 f = 100khz -100 crosstalk v out = 10v p-p , r s = 20 i , c l = 1nf f = 1khz -100 db f = 10khz -90 input voltage noise density e n f = 100hz 3.5 nv/ hz f = 1khz 3 input voltage noise 0.1hz p f p 10hz 250 nv p-p input current noise density i n f = 100hz 12 pa/ hz f = 1khz 10 capacitive loading c l no sustained oscillation, a v = +1v/v 50 pf maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
4 typical operating characteristics (v cc = +15v, v ee = -15v, v cm = 0v, outputs have r l = 10k i connected to v gnd = 0v. typical values are at t a = +25 n c, unless otherwise noted.) v os histogram MAX9633 toc01 v os (v) occurrences (%) 180 100 140 -100 -60 -20 20 60 -140 5 10 15 20 25 30 35 40 45 50 0 -180 v os drift (v/c) frequency (%) 0.5 0.4 0.2 0.3 -0.3 -0.2 -0.1 0 0.1 -0.4 5 10 15 20 25 30 35 40 45 50 0 -0.5 v os drift histogram MAX9633 toc02 supply current vs. supply voltage MAX9633 toc03 supply voltage (v) supply current (ma) 35 30 25 20 15 10 5 1 2 3 4 5 6 0 04 0 t a = +125c t a = +85c t a = +25c t a = -40c t a = 0c input offset voltage vs. input common mode input common mode (v) v os (v) 10 5 -10 -5 0 25 30 35 40 45 50 55 60 20 -15 15 t a = +125c t a = +85c t a = +25c t a = -40c t a = 0c MAX9633 toc04 input offset voltage vs. supply voltage MAX9633 toc05 supply voltage (v) v os (v) 30 20 10 25 30 35 40 45 50 55 60 20 04 0 t a = -40c t a = +25c t a = +85c t a = 0c t a = +125c bias current vs. input common mode MAX9633 toc06 input common mode (v) bias current (na) 10 5 0 -5 -10 32 34 36 38 40 42 44 46 48 50 30 -15 15 t a = -40c t a = +125c t a = 0c t a = +25c t a = +85c bias current vs. supply voltage MAX9633 toc07 supply voltage (v) 35 30 20 25 10 15 5 04 0 bias current (na) 32 34 36 38 40 42 44 46 48 50 30 t a = -40c t a = +125c t a = 0c t a = +25c t a = +85c MAX9633 toc08 120 100 -40 -20 0 40 60 20 80 -60 140 -140 -120 -100 -80 -60 -40 -20 -160 dc common-mode rejection ratio vs. temperature 0 temperature (c) cmrr (db) dc psrr vs. temperture MAX9633 toc09 temperature (c) psrr (db) 100 75 25 50 0 -25 -140 -120 -100 -80 -60 -40 -20 0 -50 125 maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
5 typical operating characteristics (continued) (v cc = +15v, v ee = -15v, v cm = 0v, outputs have r l = 10k i connected to v gnd = 0v. typical values are at t a = +25 n c, unless otherwise noted.) common-mode rejection ratio vs. frequency MAX9633 toc10 frequency (khz) cmrr (db) 10,000 1000 100 10 1 -100 -80 -60 -40 -20 0 -120 0.1 100,000 power-supply rejection ratio vs. frequency MAX9633 toc11 frequency (khz) psrr (db) 10,000 1000 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100,000 open-loop gain vs. frequency MAX9633 toc12 frequency (khz) open-loop gain (db) 1000 10 0.1 0 20 40 60 80 100 120 140 160 -20 0.001 100,000 r iso = 20 i c load = 1nf small-signal unity gain vs. frequency MAX9633 toc13 frequency (khz) gain (db) 10,000 1000 100 -15 -10 -5 0 5 10 15 20 -20 10 100,000 large-signal unity gain vs. frequency MAX9633 toc14 frequency (khz) gain (db) 100,000 10,000 10 100 1000 -15 -10 -5 0 5 10 15 20 -20 1 1,000,00 0 input refered voltage noise vs. frequency MAX9633 toc15 frequency (hz) input refered voltage noise (nv/hz) 10k 1k 11 0 100 5 10 15 20 25 30 35 40 0 0.1 100k 0.1hz to 10hz noise vs. time MAX9633 toc16 100nv/div 10s/div current noise vs. frequency MAX9633 toc17 frequency (hz) current noise (pa/hz) 10k 1k 100 10 1 20 40 60 80 100 120 140 160 180 200 0 0.1 100k input inferred maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
6 typical operating characteristics (continued) (v cc = +15v, v ee = -15v, v cm = 0v, outputs have r l = 10k i connected to v gnd = 0v. typical values are at t a = +25 n c, unless otherwise noted.) small-signal step response vs. time MAX9633 toc18 out_ 100mv/div 1s/div in_+ 100mv/div capacitive load vs. isolation resistor MAX9633 toc20 r iso (i) c load (pf) 10 100 1000 10,000 10 1 100 unstable stable thd vs. output voltage frequency = 10khz MAX9633 toc22 output voltage (v p-p ) total harmonic distortion (db) 9 8 1 2 3 5 6 4 7 01 0 -135 -130 -125 -120 -110 -115 -105 -100 -140 large-signal step response vs. time MAX9633 toc19 out_ 2v/div in_+ 2v/div 1s/div total harmonic distortion vs. frequency v out = 10v p-p MAX9633 toc21 frequency (hz) total harmonic distiortion (db) 10k 1k 100 -150 -140 -130 -120 -110 -100 -160 10 100k crosstalk vs. frequency MAX9633 toc23 frequency (khz) crosstalk (db) 10,000 1000 100 10 1 -120 -100 -80 -60 -40 -20 0 -140 0.1 100,000 maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
7 typical operating characteristics (continued) (v cc = +15v, v ee = -15v, v cm = 0v, outputs have r l = 10k i connected to v gnd = 0v. typical values are at t a = +25 n c, unless otherwise noted.) output voltage high vs. source current MAX9633 toc24 i source (ma) v oh (v) 35 30 5 10 15 20 25 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 11.0 04 0 t a = +85c t a = +125c t a = -40c t a = 0c t a = +25c 100mv step response with c load MAX9633 toc26 100mv/div 200ns/div no c load c load = 50pf c load = 100pf c load = 150pf output impedance vs. frequency MAX9633 toc28 frequency (hz) output impedance (i) 10k 1k 100 10 1 0.1 1 10 100 0.01 0.1 100k output voltage low vs. sink current MAX9633 toc25 i sink (ma) v ol (v) 35 30 5 10 15 20 25 -15.1 -15.0 -14.9 -14.8 -14.7 -14.6 -14.5 -14.4 -15.2 04 0 t a = +85c t a = +125c t a = -40c t a = 0c t a = +25c 2v step response with c load MAX9633 toc27 1v/div 200ns/div no c load c load = 50pf c load = 100pf c load = 150pf maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
8 pin description pin configuration 12 3 87 4 65 tqfn-ep v cc outb inb- + outa ina- ina+ v ee inb+ ep* *ep = exposed pad. connect to v ee externally or leave unconnected. top view so-ep top view MAX9633 MAX9633 v ee 1 2 ina- ina+ outa 3 4 inb- inb+ 8 7 v cc outb 6 5 + ep* pin name function 1 outa output a 2 ina- negative input a 3 ina+ positive input a 4 v ee negative supply voltage. bypass with a 0.1 f f capacitor to ground. 5 inb+ positive input b 6 inb- negative input b 7 outb output b 8 v cc positive supply voltage. bypass with a 0.1 f f capacitor to ground. ep exposed pad. connect to v ee externally or leave unconnected. maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
9 detailed description the MAX9633 is designed in a new 36v, high-speed complementary bicmos process that is optimized for excellent ac dynamic performance combined with high- voltage operation. the exceptionally fast settling time, low noise, low distor - tion, high bandwidth, and low input offset voltage make the ic an excellent solution to drive (up to 18-bit)high- resolution and fast sar adcs. the MAX9633 is unity gain stable and operates either with a single supply voltage up to 36v or with dual sup - plies up to q 18v. applications information driving high-resolution sar adcs high-resolution sar adcs typically switch an input capacitor in the order of tens of pf during the track and hold phases. such capacitor switching can cause a voltage glitch at the input of the adc that behaves as a load-transient condition for the driving amplifier. in many applications, this glitch is avoided by placing an external capacitor at the adc input that is in the order of 20 to 50 times the adc input capacitor. if the adc input capaci - tor ranges from 15pf to 30pf, then the external capacitor is anything between 300pf to 1.5nf, depending on the application. an isolation resistor can be placed in series between the amplifiers output and the external capaci - tor, as shown in the typical application circuit . during the load-transient condition described, the driv - ing amplifier must be able to settle to 0.5 x lsb within the adc acquisition time (t acq ). assuming a first order approximation, the number of time constants required to settle to 0.5 x lsb is a logarithm function of the number n of bits: ( ) n1 1) k l n 2 + = the external rc time constant must be such that: 2) k x r l x c < t acq as an example, consider a 16-bit sar adc with 500ns acquisition time and 20pf input capacitor. from 1): k = 12 assuming a factor of 50 for the external capacitor: c = 1nf finally, formula 2) gives: r l p 40 i the ic is optimized for very fast load-transient recovery with big capacitive loads and small isolation resistors. this makes it ideal to drive high-resolution and fast sar adcs. recommended sar adcs the MAX9633s wide supply range and fast settling make it ideal for driving high-resolution sar adcs, such as the max1320. the max1320 is a 14-bit, 8-chan - nel, simultaneous-sampling adc that measures analog inputs up to q 5v. sampling up to 250ksps per channel for eight channels, the max1320 achieves 77db snr, 90dbc sfdr, and -86db thd. the max1320s fast sample rate and typical input resistance of 8.6k i often make it necessary to have a low-noise op amp, such as the MAX9633, driving its inputs. the MAX9633 is also a good fit for an anti-aliasing active filter prior to the max1320 as shown in the typical application circuit . the max1320 is part of a family of simultaneous sampling adcs (max1316Cmax1326). other options include adcs that measure 0v to 5v inputs, or q 10v inputs, and two 4 or 8 simultaneous input channels. the max1320s high speed and resolution make it a fit for multiphase motor control and power-grid monitoring. the MAX9633 is also well-suited to drive the 16-bit max11046 8-channel, simultaneous-sampling, sar adc. the max11046 is rated for up to 250ksps. an input driver is typically not necessary at sampling rates below 100ksps. for applications that require > 100ksps sample rates, the MAX9633 offers small size, high bandwidth, and ultra-low -100db thd at 100khz. low noise and low distortion the MAX9633 is designed for applications that require very low voltage noise, making it ideal for low source impedance. when driving 16-bit sar adcs with a q 5v full-scale input, such as the max11046, the MAX9633 very low input voltage noise density specification guaran - tees 16-bit resolution up to 10mhz of signal bandwidth. the MAX9633 is also designed for ultra-low distor - tion performance. thd specifications in the electrical characteristics and typical operating characteristics is calculated up to the 5th harmonic. even when driving high voltage swing up to 10v p-p , the MAX9633 maintains excellent low distortion operation up and beyond 100khz of bandwidth. besides driving high-resolution and high-bandwidth sar adcs, applications that benefit for low-noise and low- distortion applications can be found in industrial power- grid and smart-grid, industrial motor-control, medical imaging, automated test equipment, instrumentation, and professional audio equipment. maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
10 input common mode and output swing the ics input common-mode range as well as the out - put range can swing to the negative rail v ee . these two features are very important for applications where the MAX9633 is used with a single supply (v ee connected to ground). in such a case, being able to swing the input common-mode to the negative rail offers ground-sensing capability. input differential voltage protection during normal op-amp operation, the inverting and non - inverting inputs of the ic are at essentially the same volt - age. however, either due to fast input voltage transients or due to other fault conditions, these pins can be forced to be at two different voltages. internal back-to-back diodes protect the inputs from an excessive differential voltage (figure 1). therefore, in+ and in- can be any voltage within the range shown in the absolute maximum ratings . note the protection time is still dependent on the package thermal limits. if the input signal is fast enough to create the internal diodes forward bias condition (0.7), the input signal cur - rent must be limited to 20ma or less. if the input signal current is not inherently limited, an external input series resistor can be used to limit the signal input current. care should be taken in choosing the input series resis - tor value, since it degrades the low-noise performance of the device. electrostatic discharge (esd) the ic has built-in circuits to protect from electrostatic discharge (esd) events. an esd event produces a short, high-voltage pulse that is transformed into a short current pulse once it discharges through the device. the built-in protection circuit provides a current path around the op amp that prevents it from being damaged. the energy absorbed by the protection circuit is dissipated as heat. esd protection is guaranteed up to 5kv with the human body model (hbm). the human body model simulates the esd phenomenon wherein a charged body directly transfers its accumu - lated electrostatic charge to the esd-sensitive device. a common example of this phenomenon is when a person accumulates static charge by walking across a carpet and then transfers all of the charge to an esd-sensitive device by touching it. power supplies and layout the ic can operate with dual supplies from q 2.25v to q 18v or with a single supply from +4.5v to +36v with respect to ground. when used with dual supplies, bypass both v cc and v ee with their own 0.1 f f capaci - tor to ground. when used with a single supply, bypass v cc with a 0.1 f f capacitor to ground. careful layout technique helps optimize performance by decreasing the amount of stray capacitance at the op amps inputs and outputs. to decrease stray capacitance, minimize trace lengths by placing external components close to the op amps pins. for high-frequency designs, ground vias are critical to provide a ground return path for high-frequency signals and should be placed around the signal traces and near the decoupling capacitors. signal routing should be short and direct to avoid parasitic effects. avoid using right angle connectors since they may introduce a capacitive discontinuity and ultimately limit the fre - quency response. chip information process: bicmos figure 1. input protection circuit maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
11 package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so-ep s8e+14 21-0111 90-0151 8 tdfn-ep t833+3 21-0137 90-0060 maxim integrated dual 36v op amp for 18-bit sar adc front-end MAX9633
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 12 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2015 maxim integrated maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/10 initial release 1 1/11 added so-ep package 1, 2, 8, 11 2 5/14 corrected package information 11 3 8/14 corrected esd protection in features and electrostatic discharge (esd) sections 1, 10 4 1/15 updated benefits and features section 1 dual 36v op amp for 18-bit sar adc front-end MAX9633

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